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Virtual Prototyping for SoC Based Designs - Is this the need of the hour? |
| Speaker | Dr.
Suryaprasad Jayadevappa Motorola Inc. |
| Time/Location |
10 December 2004,11:30
to 1:00 PM |
| Abstract |
The combination of intense time-to-market pressures and the relentless growth in design size and complexity has rendered old development models inefficient and impractical. In times of shortened product life cycles and increased product complexity it has become necessary to define, design and test the features of a forthcoming product prior to creation of any physical prototypes. Several surveys have shown that more than half of all chips require at least one revision to fix bugs before product release. It is estimated that the cost of a chip turn/respin at submicron geometries can be well over a million dollars. Unexpected silicon turns can kill a project, either because the company simply can't afford the extra cost or because the schedule delay means that the product would completely miss its market window. A new approach is needed to ensure that hardware design takes place within the context of system-level requirements and in turn facilitates early software development. This presentation covers some background on the evolving role of hardware designers, and outlines the requirements for effective performance in a world of systems-on-chip (SoC). The technology of virtual prototyping(VP), traditionally seen as tools for system architects and software engineers, discusses the benefits that virtual prototypes confer upon hardware designers and software developers as well. A virtual prototype platform is a software-simulation-based, architectural-level model of the electronic system. Many studies demonstrate that the result of adopting a virtual prototype-based development process results in a higher quality product, and are delivered to the market faster. Virtual prototyping has a number of unique advantages over its physical counterpart. It features unsurpassed flexibility and avoids board or silicon iterations when coping with change or design derivatives. Virtual platform can effectively contribute to lowering the risk and decreasing the TTM, through early software development and integration. |
| Biography | Dr. Jayadevappa received his Ph.D in Computer Engineering from Florida Atlantic University in 2003. He has worked earlier with Cadence Design Systems, San Jose for two years and is currently working at Motorola after graduating. He has over eight years of teaching experience. His main research interests include System Level Design Methodologies, Embedded System Design, Hardware-Software Co-Design and Virtual Prototyping. |
| Map/Directions |
From I95, exit at
Glades Rd (Exit 45) and drive east, staying in left lane. Drive 1/2
mile and left at light (NW 10th Ave). This is Broward Blvd on the campus.
**PARKING STRICTLY ENFORCED** Do not park in lots requiring decals.
Tickets will be issued. There is parking information booth on the right
after entering campus. |
